The present invention generally relates to an operation circuit based on a floating-point representation.
Generally, the fixed-point representation system is not, capable of representing an extremely large number, because of the narrow span of numbers which can be represented by the fixed-point representation system. Additionally, in most cases, the fixed-point representation system handles only an integer. For these reasons, it is required to provide another representation system for representing real numbers, as is necessary for operation for use in science and technology. From this viewpoint, a floating-point representation system has been proposed, in which two numbers called an exponent and a mantissa are combined.
A general floating-point number is represented as follows: EQU -1).sup.s .multidot.m.multidot.R.sup.e ( 1)
where `R` is the radix and `s` denotes the sign. When the sign is positive, s=0, and on the other hand, when the sign is negative, s=1. Further, `m` and `e` are the mantissa and the exponent, respectively. The floating-point representation system is constructed by combining the representation of formula (1) and the fixed-point representation. It is noted that the effective length of the digits depends on the length of the mantissa. For this reason, when it is desired to represent numbers with high precision, a representation system is employed such that an increased length of the mantissa part is used.
The floating-point operation can provide a wide dynamic range and high precision, compared with integer operation. Particularly, the recent trend exhibits the requirement of high-speed operation capable of satisfying requirements for a variety of high-level operations.
A conventional floating-point operation circuit for processing two input operands includes selectors, an exponent part comparator, a shifter, an arithmetic and logic unit (hereafter simply referred to as an ALU), and a complementer. The input operands pass through the exponent part comparator, the shifter, the ALU and the complementer without exception. However, it is noted that there are some cases where some operands are not required to be passed through all the parts. Particularly, an amount of delay occurring in the shifter and the complementer is about same as that for the ALU. From this viewpoint, there exists a delay in signal processing in the conventional floating-point operation circuit. Such a delay prevents high-speed floating-point operation.